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CadenceCONNECT:
Technology Forum 2025
Hyderabad
Summary
Join us at the Cadence Technology Hyderabad on June 11, 2025. Discover how Cadence solutions can address your toughest custom, digital, and verification design challenges while improving speed and profitability.
This full-day event will feature:
- Expert insights – Discover the latest Cadence products, flows, and methodologies to enhance the development of silicon, SoCs, and systems, enabling you to create advanced technologies faster and more profitably.
- Best practices shared by your peers on how they are using Cadence technologies effectively.
- Interactive discussions with Cadence R&D team members on technology, roadmaps, and use cases.
The event will feature three tracks covering Custom and Analog Design, Digital Design, and System Design and Verification.
Event Details:
Date: June 11, 2025
Time: 9:00AM - 4:30PM
Location: Novotel Hyderabad Convention Centre (HICC), HITEC City, Hyderabad
| Digital Design and Signoff Track | |
| Timing | Topic |
| 9:00 - 10:00 | Registration |
| 10:00 - 10:30 | Cadence Keynote |
| 10:30 - 11:15 | Advanced Techniques for Full-Flow PPA Optimization |
| 11:15 - 11:30 | Tea Break |
| 11:30 - 12:00 | Cadence Certus Timing Closure Solution and Tempus 25.1 Technology Update |
| 12:00 - 12:30 | Joules RTL Studio |
| 12:30 - 13:00 | User Presentation |
| 13:00 - 14:00 | Lunch Break |
| 14:00 - 15:00 | Next Generation Cerebrus: AI-Driven Multi-Block / SoC Design Platform |
| 15:00 - 15:30 | Accelerate IR Signoff with Voltus InsightAI |
| 15:30 - 16:00 | User Presentation |
| 16:00 - 16:30 | 24x7 Support and Learning System – A Round-the-Clock Problem Solver |
| System Design and Verification Track | |
| Timing | Topic |
| 9:00 - 10:00 | Registration |
| 10:00 - 10:30 | Cadence Keynote |
| 10:30 - 11:00 | Cadence Technology Overview - Vision and Roadmap |
| 11:00 - 11:15 | Tea Break |
| 11:15 - 12:00 | Panel Discussion: The Autonomous Future – Exploring AI's Role in Problem-Solving and Innovation |
| 12:00 - 12:45 | Xcelium Apps: Enhancing Verification with Essential, Time-Saving Simulation Solutions |
| 12:45 - 13:15 | 24x7 Support and Learning System – A Round-the-Clock Problem Solver |
| 13:15 - 14:00 | Lunch Break |
| 14:00 - 14:30 | Verisium Transforming Debugging from Tedious to Triumph |
| 14:30 - 15:00 | Jasper Apps: What’s new? |
| 15:00 - 15:45 | FMEDA-Driven Safety Verification – Full Flow Overview with Success Stories |
| 15:45 - 16:30 | Palladium Z3 and Protium X3 Systems - A New Era of Accelerated Verification, Software Development and Digital Twins |
| Custom and Analog Design Track | |
| Timing | Topic |
| 9:00 - 10:00 | Registration |
| 10:00 - 10:30 | Cadence Keynote |
| 10:30 - 11:15 | Accelerating Custom Designs and Implementation with AI-Based Automation |
| 11:15 - 11:30 | Tea Break |
| 11:30 - 12:00 | New Generation Multi-Mode Simulations for High-Reliability Applications |
| 12:00 - 12:30 | Intelligent Parasitic Analysis to Reach Faster Design Goals |
| 12:30 - 13:15 | Panel Discussion: AI Potential in Custom/Analog Designs |
| 13:15 - 14:15 | Lunch Break |
| 14:15 - 14:45 | 24x7 Support and Learning System – A Round-the-Clock Problem Solver |
| 14:45 - 15:15 | User Presentation - Micron |